The present application relates to bidirectional bipolar transistors, and more particularly to power converters which incorporate bidirectional bipolar transistors, and also to related methods.
Note that the points discussed below may reflect the hindsight gained from the disclosed inventions, and are not necessarily admitted to be prior art.
Power Packet Switching Converters
A new kind of power converter was disclosed in U.S. Pat. No. 7,599,196 entitled “Universal power conversion methods,” which is incorporated by reference into the present application in its entirety. This patent describes a bidirectional (or multidirectional) power converter which pumps power into and out of a link inductor which is shunted by a capacitor.
The switch arrays at the ports are operated to achieve zero-voltage switching by totally isolating the link inductor+capacitor combination at times when its voltage is desired to be changed. (When the inductor+capacitor combination is isolated at such times, the inductor's current will change the voltage of the capacitor, as in a resonant circuit. This can even change the sign of the voltage, without loss of energy.) This architecture is now referred to as a “current-modulating” or “Power Packet Switching” architecture. Bidirectional power switches are used to provide a full bipolar (reversible) connection from each of multiple lines, at each port, to the rails, i.e. the internal lines across which the link inductor and its capacitor are connected.
FIG. 21 shows a sample embodiment of a Full-Bridge Buck-Boost Converter in a Three Phase AC Full Cycle Topology with Bi-directional Conducting and Blocking Switches (BCBS). Each BCBS is shown as appears in FIG. 2 of U.S. Pat. No. 5,977,569. Input filter capacitors 2130 are placed between the input phases and output filter capacitors 2131 similarly attached between the output phases in order to closely approximate voltage sources and to smooth the current pulses produced by the switches and the inductor 2120. Output filter capacitors are preferably attached in a grounded Y configuration as shown. An input line reactor 2132 may be needed in some applications to isolate the voltage ripple on the input capacitors 2130 from the utility 2122.
Referring to FIG. 21, illustrated is a schematic of a three phase converter 2100. The converter 2100 is connected to a first and second power portals 2122 and 2123 each of which may source or sink power, and each with a port for each phase of the portal. It is the function of said converter 2100 to transfer electric power between said portals while accommodating a wide range of voltages, current levels, power factors, and frequencies between the portals. Said first portal may be for example, a 460 VAC three phase utility connection, while said second portal may be a three phase induction motor which is to be operated at variable frequency and voltage so as to achieve variable speed operation of said motor. This may also accommodate additional portals on the same inductor, as may be desired to accommodate power transfer to and from other power sources and/or sinks.
Converter 2100 is comprised of a first set of electronic switches S1u, S2u, S3u, S4u, S5u, and S6u that are connected between a first port 2113 of a link inductor 2120 and each phase, 2124 through 2129, of the input portal, and a second set of electronic switches S1l, S2l, S3l, S4l, S5l, and S6l that are similarly connected between a second port 2114 of link inductor 2120 and each phase of the output portal. A link capacitor 2121 is connected in parallel with the link inductor, forming the link reactance. Each of these switches is capable of conducting current and blocking current in both directions, and may be composed of the bi-directional IGBT of FIG. 2 of U.S. Pat. No. 5,977,569. Many other such bi-directional switch combinations are possible, such as anti-parallel reverse blocking IGBTs.
The converter 2100 also has input and output capacitor filters 2130 and 2131, respectively, which smooth the current pulses produced by switching current into and out of inductor 2120. Optionally, a line reactor 2132 may be added to the input to isolate the voltage ripple on input capacitor filter 2131 from the utility and other equipment that may be attached to the utility lines. Similarly, another line reactor, not shown, may be used on the output if required by the application.
For illustration purposes, assume that power is to be transferred in a full cycle of the inductor/capacitor from the first to the second portal, as is illustrated in FIG. 24. Also assume that, at the instant the power cycle begins, phases Ai and Bi have the highest line to line voltage of the first (input) portal, link inductor 2120 has no current, and link capacitor 2121 is charged to the same voltage as exists between phase Ai and Bi. The controller now turns on switches S1u and S2l, whereupon current begins to flow from phases Ai and Bi into link inductor 2120, shown as Mode 1 of FIG. 23A. FIG. 24 shows the inductor current and voltage during the power cycle of FIGS. 23A-23J, with the Conduction Mode sequence 2400 corresponding to the Conduction Modes of FIGS. 23A-23J. The voltage on the link reactance remains almost constant during each mode interval, varying only by the small amount the phase voltage changes during that interval. After an appropriate current level has been reached, as determined by a controller to achieve the desired level of power transfer and current distribution among the input phases, switch S2l is turned off. Current now circulates, as shown in FIG. 23B, between link inductor 2120 and link capacitor 2121, which is included in the circuit to slow the rate of voltage change, which in turn greatly reduces the energy dissipated in each switch as it turns off. In very high frequency embodiments, the capacitor 2121 may consist solely of the parasitic capacitance of the inductor and/or other circuit elements.
To continue with the cycle in FIG. 23B, shown as Mode 2 in FIG. 24, switch S3l is next enabled, along with the previously enabled switch S1u. As soon as the link reactance voltage drops to just less than the voltage across phases Ai and Ci, which are assumed for this example to be at a lower line-to-line voltage than phases Ai and Bi, switches S1u and S3l become forward biased and start to further increase the current flow into the link inductor, and the current into link capacitor temporarily stops. The two “on” switches, S1u and S3l, are turned off when the desired peak link inductor current is reached, said peak link inductor current determining the maximum energy per cycle that may be transferred to the output. The link inductor and link capacitor then again exchange current, as shown in FIG. 23C, with the result that the voltage on the link reactance changes sign, as shown in graph 2401, between modes 2 and 3 of FIG. 24. Now as shown in FIG. 23D, output switches S5u and S6l are enabled, and start conducting inductor current into the motor phases Ao and Bo, which are assumed in this example to have the lowest line-to-line voltages at the present instance on the motor. After a portion of the inductor's energy has been transferred to the load, as determined by the controller, switch S5u is turned off, and S4u is enabled, causing current to flow again into the link capacitor, which increases the link inductor voltage until it becomes slightly greater than the line-to-line voltage of phases Ao and Co, which are assumed in this example to have the highest line-to-line voltages on the motor. As shown in FIG. 23E, most of the remaining link inductor energy is then transferred to this phase pair (into the motor), bringing the link inductor current down to a low level. Switches S4u and S6l are then turned off, causing the link inductor current again to be shunted into the link capacitor, raising the link reactance voltage to the slightly higher input line-to-line voltage on phases Ai and Bi. Any excess link inductor energy is returned to the input. The link inductor current then reverses, and the above described link reactance current/voltage half-cycle repeats, but with switches that are complementary to the first half-cycle, as is shown in FIGS. 23F to 23J, and in Conduction Mode sequence 2400, and graphs 2401 and 2402. FIG. 23G shows the link reactance current exchange during the inductor's negative current half-cycle, between conduction modes.
FIG. 22 summarizes the line and inductor current waveforms for a few link reactance cycles at and around the cycle of FIGS. 23A-23J and 24.
Note that TWO power cycles occur during each link reactance cycle: with reference to FIGS. 23A-23J, power is pumped IN during modes 1 and 2, extracted OUT during modes 3 and 4, IN again during modes 5 and 6 (as in FIGS. 23F-23H), and OUT again during modes 7 and 8 (as in FIGS. 231-23J). The use of multi-leg drive produces eight modes rather than four, but even if polyphase input and/or output is not used, the presence of TWO successive in and out cycles during one cycle of the inductor current is notable.
As shown in FIGS. 23A-23J and FIG. 24, Conduction Mode sequence 2400, and in graphs 2401 and 2402, the link reactance continues to alternate between being connected to appropriate phase pairs and not connected at all, with current and power transfer occurring while connected, and voltage ramping between phases while disconnected (as occurs between the closely spaced dashed vertical lines of which 2403 in FIG. 24 is one example).
The conventional epitaxial base NPN transistor has an N+ region over the entire back surface. This necessarily prevents the structure from having the same electrical characteristics in each direction when operated as a bidirectional transistor. These structures are therefore not well-suited to acting as bidirectional switches in power-packet-switching power converter architectures.
Semiconductor statistics under high level non-equilibrium carrier densities can be quite different from low level carrier densities. Conventional recombination is generally less relevant with high level carrier density than in low level conditions. Typical definitions of carrier lifetime are also less relevant. Carriers can often interact directly in high level conditions through Auger interactions. The beta (ratio of emitter current to base current) will therefore normally decrease as a bipolar transistor is driven into high level non-equilibrium carrier densities. These densities can be, for example, more than two orders of magnitude above intrinsic carrier density.
The voltage drop under conditions of high level non-equilibrium carrier concentration will be low, even if the resistivity under small currents is large. Thus a device can be optimized to withstand high voltages (e.g. 1200V or more) while still achieving a forward voltage drop of less than a Volt.